The organization of the paper is follows.
A realistic fault injection system must have the capability to access most signals within a VHDL description including the inputs and outputs of the description this is crucial for both onand off-line testing.
MODELSIM XE II 5.7 G PORTABLE
Incorporating an injection technique in a VHDL description instead of the simulation code is more easily handled and is portable between design packages. Other papers approached fault injection differently by using methodologies based on scan paths, using outside logic sources to inject faults into VHDL descriptions, or by modifying existing circuit architecture. involve injection techniques that must be used within simulation VHDL. Other approaches such as the one offered by Parrotta et al. proposed a technique to accomplish the same goal, offering a different approach to fault injection.
MODELSIM XE II 5.7 G SOFTWARE
This maintains the system as platform independent, able to simulate on any VHDL simulation software without extensive knowledge of simulation VHDL, which is a very tedious approach. The fault injection system proposed in this paper will be contained within the instruction VHDL of a system. Any internal signal can be accessed at the VHDL level for the purposes of injecting faults, thus ensuring greater controllability and observability of the system. For (offline) testable systems fault injection helps in evaluating the testability of the entire system before the system is actually implemented. They can be both transient and permanent in nature. Faults in an online testable system are assumed to be mainly single bit faults where a single bit is flipped from a logic 1 to a 0 or vice-versa. It enables a designer to test whether the functional circuit and the checker within the system are operating as specified. These features enable the performance of a circuit or a system under faulty conditions to be effectively evaluated before it is implemented.įault injection is crucial in an online testable system. In addition the ability to insert permanent faults on single bits or a data word must also be taken into consideration. The ability to simulate the occurrence of a transient fault in the VHDL description of a circuit is extremely important if the circuit has built-in on-line fault detection capability. Some work has been reported on the development of VHDL model for intermittent faults, however not much has been reported on transient (soft) fault injection in VHDLbased circuit descriptions. Temporary faults can be one of two types: intermittent and transient.
MODELSIM XE II 5.7 G OFFLINE
Permanent faults that exist in logic circuits are normally identified during offline testing by the manufacturer of ICs, temporary faults on the other hand are of major concern after an IC chip is used in a particular application. In general, faults are grouped into two categories: permanent and temporary. The injection technique allows faults to be injected at varying levels of VHDL hierarchy and hence help in evaluating the performance of a testable system.
A fault injection system provides the capability of introducing a fault at any desired location into the VHDL model of a circuit. The capability to ascertain the testability of a system at the VHDL level before it is implemented, allows design modifications to achieve the desired goal. testability, power consumption, need to be evaluated. Several important criteria of a system to be designed e.g. The actual implementation of the system is then performed using this specification. Modern digital systems are typically specified in a high level language such as VHDL.
This capability of inserting transient and permanent faults should help in evaluating the testability of a digital system before it is actually implemented. Access to all VHDL blocks a system is straight forward using a specially designed single fault injection block. This paper presents a technique for transient and permanent fault injection at the VHDL level description of both combinational and sequential digital circuits. This feature enables designers to verify the fault detection capability of online as well as offline testable digital circuits for both permanent and transient faults, during the design stage of the circuits. The ability to evaluate the testability of digital circuits before they are actually implemented is critical for designing highly reliable systems. Keywords: On-Line Fault Detection VHDL Transient Faults Fault Injection LFSR Department of Electrical Engineering, Texas A&M University, Texarkana, USAĮmail: Janurevised Maaccepted March 16, 2012
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